- To establish process integration flow for 2.5D and 3D IC stacking using Wafer-to-Wafer and Chip-to-Wafer Bonding technologies.
- Development of processes (e.g. Wafer-to-Wafer temporary bonding) in 2.5D/3D integration.
- Establish process integration flow for 2.5D and 3D IC stacking using various Bonding technologies.
- Process fabrication of 2.5D/3D packages.
- Present the research work in world class prestigious conferences and Journals.
- Work with industry partners and multidisciplinary team members in execution of R&D projects.
- Bachelor or Masters in Electronic / Microelectronics / Material Engineering .
- Good Knowledge on semiconductor backend processes in particular wafer bonding processes.
- Knowledge of advanced packaging technologies such as 3D IC stacking, FOWLP would be an advantage.
- Good analytical, communication and presentation skills.
- No experience required