Lead Research Engineer (Multi Chiplet Heterogeneous Integration and High-Speed IO Designer), (SiP), IME
Posting Date : 16 May 2025 | Closing Date :28 Feb 2026
The above eligibility criteria are not exhaustive. A*STAR may include additional selection criteria based on its prevailing recruitment policies. These policies may be amended from time to time without notice. We regret that only shortlisted candidates will be notified.
|
Type of Employment
|
:
|
|
Full-Time
|
|
Minimum Experience
|
:
|
|
2 Years
|
|
Work Location
|
:
|
|
Fusionopolis
|
|
|
|
|
|
|